Logic circuitry, such as that found within various portions (e.g., a processor) of a data processing system, typically incorporates circuitry for enabling the designer and manufacturer of the logic circuitry to test the accuracy of the logic circuitry. Logic circuitry typically comprises various stages of combinatorial logic circuits, where each stage outputs data to a register for temporary storage before passage to a next stage of combinatorial logic circuits. One way of testing these various stages of combinatorial logic is to scan values into the registers, allow these values to propagate through the combinatorial logic into a register at the output, and to scan out the results from the output register to verify that the combinatorial logic circuits perform their specified logic operations on the inputted data.
A common technique for scanning values into and out of registers is to utilize a scan register, which during normal operation, operates as a normal register to pass data from one stage of combinatorial logic circuits to another. These scan registers, during a testing mode, allow for the input and output of data values while disabling the normal operational mode of these registers.
Typical scan register 60 is shown in FIG. 6. The master portion of register 60 includes devices 61-64, while a slave portion of register 60 includes devices 65-67. Devices 61-67 each include an inverter circuit with devices 61, 62, 64, 65 and 67 being tri-statable devices. Device 61 passes data on the high (logical "1" or asserted) portion of a clock (CLK) signal while device 64 passes data on the low (logical "0" or negated) portion of the CLK signal. Device 62 passes data on the high portion of a scan clock (SCLK) signal, while device 64 may also pass data on the low portion of the SCLK signal. Device 65 passes data on the high portion of signal CLK.sub.-- SCLK.sub.-- B signal, which means that either the CLK or the SCLK clock signals will activate device 65. Device 67 passes data during the low portion of the CLK.sub.-- SCLK.sub.-- B signal. In one embodiment of the present invention, the CLK.sub.-- SCLK.sub.-- B signal is formed as the Boolean NOR function of the CLK signal and the SCLK signal (i.e. the CLK.sub.-- SCLK.sub.-- B signal is active only when both the CLK signal and the SCLK signal are inactive). Device 61 receives data (Din), which may originate within some stage of combinatorial logic. Device 62 receives scan data (Sin), which may be received from scan control logic (discussed further below) or from a previous scan register. Device 66 outputs either regular data (Dout), or scan data (Sout).
The master portion of register 60 latches either the Din signal or the Sin signal, during the active high portion of the corresponding clock signal. This data is then transferred to the slave portion of scan register 60 during the low phase of the corresponding clock signal. The master operation is controlled by either the CLK signal (for Din) or the SCLK signal (for Sin). The slave portion is controlled by the CLK.sub.-- SCLK.sub.-- B signal, which latches the master data, transferring it to the Dout/Sout signal.
A scan chain is formed by connecting the Sout signal of one scan register to the Sin signal of a next scan register in the scan chain. Once all registers are tied together, the Sin signal of the first register in the scan chain is the input from scan control logic, and the Sout signal of the last register becomes the output of the scan chain. Serial data is fed into and taken out of the scan chain to read and write the parallel Din and Dout signals, respectively.
During scan mode, which is used to set up data into registers and read out the previously captured data, the scan clocks are used. When the SCLK signal becomes active, Sin data is loaded into the master portion of a scan register. The CLK.sub.-- SCLK.sub.-- B signal acts as an active low signal of SCLK, loading the data from the master to the slave, and placing the scan data at the output when the CLK.sub.-- SCLK.sub.-- B signal goes low. In this mode, the CLK signal is held inactive, so that the Din signal does not collide with the Sin signal. One can consider the master portion of scan register 60 as performing a clocked multiplexor latch operation. Note that the SCLK and CLK signals do not need to be generated from the same clock signal. For example, scan registers may use opposite phases of a clock to drive the CLK and SCLK signals if cycle isolation between normal mode and scan mode is used. In addition, the CLK and SCLK signals may be driven by clocks of different frequencies.
During normal operation of register 60, the SCLK signal is held inactive and the CLK signal toggles and functions as the clock for the master portion of scan register 60. The CLK.sub.-- SCLK.sub.-- B signal toggles and functions as the clock for the slave portion of scan register 60, advancing the latched Din signal to the slave portion of register 60. The CLK.sub.-- SCLK.sub.-- B signal is active in both modes because the data from the master is the same for both cases.
Since the data output (Dout) and the scan output (Sout) of scan register 60 are a shared signal, the scan routing loads the output of register 60. This creates an excess load, impacting both the speed and energy consumption of register 60. Since the scan chain loading depends on the placement of the registers within an integrated circuit, and the order in which the registers are connected, the loading can be much higher than the loading for the Dout signal. For example, the Sout signal from one scan register may be routed to the Sin signal of another scan register a considerable distance apart, requiring that larger devices be implemented within the scan registers in order to drive the signal through the long scan route. Larger devices also result in an impact on the required area within an integrated circuit.
As a result of the foregoing, there is a need in the art for an improved scan register that lessens the impact on the speed and energy consumption of the register and the semiconductor area needed to implement such a scan register.